62 lines
2.0 KiB
INI
62 lines
2.0 KiB
INI
# SPDX-License-Identifier: BSD-3-Clause
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# Copyright (C) 2022 by NanoXplore, France - all rights reserved
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#
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# configuration file for NG-Ultra SoC from NanoXplore.
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# NG-Ultra is a quad-core Cortex-R52 SoC + an FPGA.
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#
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transport select jtag
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adapter speed 10000
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME NGULTRA
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}
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if { [info exists CHIPCORES] } {
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set _cores $CHIPCORES
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} else {
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set _cores 4
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}
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set DBGBASE {0x88210000 0x88310000 0x88410000 0x88510000}
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set CTIBASE {0x88220000 0x88320000 0x88420000 0x88520000}
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# Coresight access to the SoC
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jtag newtap $_CHIPNAME.coresight cpu -irlen 4 -expected-id 0x6BA00477
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# Misc TAP devices
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jtag newtap $_CHIPNAME.soc cpu -irlen 7 -expected-id 0xFAAA0555
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jtag newtap $_CHIPNAME.pmb unknown1 -irlen 5 -expected-id 0xBA20A005
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jtag newtap $_CHIPNAME.fpga fpga -irlen 4 -ignore-version -ignore-bypass
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# Create the Coresight DAP
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dap create $_CHIPNAME.coresight.dap -chain-position $_CHIPNAME.coresight.cpu
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for { set _core 0 } { $_core < $_cores } { incr _core } {
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cti create cti.$_core -dap $_CHIPNAME.coresight.dap -ap-num 0 \
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-baseaddr [lindex $CTIBASE $_core]
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if { $_core == 0} {
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target create core.$_core armv8r -dap $_CHIPNAME.coresight.dap \
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-ap-num 0 -dbgbase [lindex $DBGBASE $_core] -cti cti.$_core
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} else {
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target create core.$_core armv8r -dap $_CHIPNAME.coresight.dap \
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-ap-num 0 -dbgbase [lindex $DBGBASE $_core] -cti cti.$_core -defer-examine
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}
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}
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# Create direct APB and AXI interfaces
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target create APB mem_ap -dap $_CHIPNAME.coresight.dap -ap-num 0
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target create AXI mem_ap -dap $_CHIPNAME.coresight.dap -ap-num 1
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lappend post_init_commands {
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foreach t [target names] {
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set dap [$t cget -dap]
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set ap [$t cget -ap-num]
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$dap apsel $ap
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# speed up firmware upload by reducing nb of RUNTEST cycles
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echo "NGUltra post-init: $dap AP.$ap set memaccess to 5"
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$dap memaccess 5
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}
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}
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