LuChiChick 2b73c30a9d Split the UNTRUSTED_FLASH into the .untrusted_text and .untrusted_rodata sections for code and read-only data storage.

2026-09-14 15:56:05 +08:00

Core

commit for SPI1 config, working on 32 Mbit/s speed with low clock polarity (CPOL) and first edge clock phase (CPHA); PB3 has now been set as SPI1_CS pin with named user label, working on push pull mode.

2026-09-14 10:27:29 +08:00

Drivers

commit for SPI1 config, working on 32 Mbit/s speed with low clock polarity (CPOL) and first edge clock phase (CPHA); PB3 has now been set as SPI1_CS pin with named user label, working on push pull mode.

2026-09-14 10:27:29 +08:00

Middlewares/Third_Party/FreeRTOS/Source

commit for FreeRTOS config with 4K heap and 64 words minimal stack size based on CMSIS_V1 interface.

2026-08-04 14:54:10 +08:00

.gitattributes

commit for .gitattributes rules.

2026-08-03 19:26:34 +08:00

.gitignore

commit for .gitignore rules.

2026-08-03 19:29:26 +08:00

startup_stm32g030xx.s

commit for a very basic initial project with SWD port config.

2026-08-03 19:49:55 +08:00

STM32G030F6P6_Evaluation.ioc

commit for SPI1 config, working on 32 Mbit/s speed with low clock polarity (CPOL) and first edge clock phase (CPHA); PB3 has now been set as SPI1_CS pin with named user label, working on push pull mode.

2026-09-14 10:27:29 +08:00

STM32G030xx_FLASH.ld

Split the UNTRUSTED_FLASH into the .untrusted_text and .untrusted_rodata sections for code and read-only data storage.

2026-09-14 15:56:05 +08:00

S

Description

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4.4 MiB

Languages

C 97.2%

Tcl 2.4%

Makefile 0.2%

Assembly 0.1%