Import xPack OpenOCD 0.12.0-7 and GNU Make 4.4.1 from x86_64-w64-mingw32.

2026-09-14 16:20:05 +08:00
parent 2b73c30a9d
commit 534c017e0f
1133 changed files with 74341 additions and 0 deletions
@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# SpacemiT Key Stone K1 target
+#
+# https://www.spacemit.com/key-stone-k1
+#
+
+transport select jtag
+
+adapter speed 2000
+
+# Set TARGET to "rcpu" to enable JTAG for RCPU
+if { [info exists TARGET] } {
+    set _TARGET $TARGET
+} else {
+    set _TARGET x60
+}
+
+if { $_TARGET == "rcpu" } {
+    set CPUTAPID 0x10308A6D
+    set DRVAL 0xe
+} else {
+    set CPUTAPID 0x10000E21
+    set DRVAL 0xa
+}
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME k1
+}
+
+if { [info exists CORES] } {
+    set _cores $CORES
+} else {
+    set _cores 1
+}
+
+if { [info exists SECJTAG] } {
+    jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $CPUTAPID
+} else {
+    jtag newtap pre unknown -irlen 1 -expected-id 0x00000000 -disable
+    jtag configure pre.unknown -event tap-enable ""
+
+    jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $CPUTAPID -disable
+    jtag configure $_CHIPNAME.cpu -event tap-enable ""
+
+    jtag newtap post unknown -irlen 9 -expected-id 0x08501C0D -ignore-version
+
+    jtag configure post.unknown -event setup {
+        global _CHIPNAME DRVAL
+
+        irscan post.unknown 0x98
+        drscan post.unknown 16 $DRVAL
+
+        jtag tapenable pre.unknown
+        jtag tapenable $_CHIPNAME.cpu
+    }
+}
+
+set _TARGETNAME $_CHIPNAME.cpu_$_TARGET
+
+if { $_TARGET == "rcpu" } {
+    target create $_TARGETNAME.0 riscv -chain-position $_CHIPNAME.cpu
+} else {
+    set DBGBASE {0x0 0x400}
+    set _smp_command "target smp"
+
+    for { set _core 0 } { $_core < $_cores } { incr _core } {
+        target create $_TARGETNAME.$_core riscv -chain-position $_CHIPNAME.cpu \
+            -coreid [expr {$_core % 4}] -dbgbase [lindex $DBGBASE [expr {$_core / 4}]]
+
+        if { [expr {$_core % 4}] == 0 } {
+            $_TARGETNAME.$_core configure -rtos hwthread
+        }
+
+        set _smp_command "$_smp_command $_TARGETNAME.$_core"
+    }
+
+    eval $_smp_command
+}
+
+set _SPEED 8000
+
+$_TARGETNAME.0 configure -event examine-start {
+    adapter speed $_SPEED
+    puts [ adapter speed ]
+}
+
+foreach t [target names] {
+    # $t riscv set_mem_access sysbus progbuf
+    $t riscv set_mem_access progbuf
+}