Import xPack OpenOCD 0.12.0-7 and GNU Make 4.4.1 from x86_64-w64-mingw32.
This commit is contained in:
@@ -0,0 +1,86 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Nordic nRF52, nRF53 and nRF91 CTRL-AP handling
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#
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if { [using_hla] } {
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echo ""
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echo "nRF device has a CTRL-AP dedicated to recover the device from AP lock."
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echo "A high level adapter (like a ST-Link) you are currently using cannot access"
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echo "the CTRL-AP so 'nrfxx_recover' command will not work."
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echo "Do not enable UICR APPROTECT."
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echo ""
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} else {
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# Test if debug/MEM-AP is locked by UICR APPROTECT
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proc _nrf_check_ap_lock { ctrl_ap_num unlocked_value } {
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set target [target current]
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set dap [$target cget -dap]
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set err [catch {set APPROTECTSTATUS [$dap apreg $ctrl_ap_num 0xc]}]
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if {$err == 0 && $APPROTECTSTATUS < $unlocked_value} {
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echo ""
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echo "****** WARNING ******"
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echo "\[$target\] device has AP lock engaged (see UICR APPROTECT register)."
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echo "Debug access is denied."
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echo "Use 'nrfxx_recover' to erase and unlock the device."
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echo ""
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poll off
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return 1
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}
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return 0
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}
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# Mass erase and unlock the device using proprietary nRF CTRL-AP
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proc _nrf_ctrl_ap_recover { ctrl_ap_num {is_cpunet 0} } {
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set target [target current]
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set dap [$target cget -dap]
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set IDR [$dap apreg $ctrl_ap_num 0xfc]
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if {$IDR != 0x12880000} {
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echo "Error: Cannot access nRF CTRL-AP!"
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return
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}
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poll off
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# Reset and trigger ERASEALL task
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$dap apreg $ctrl_ap_num 4 0
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$dap apreg $ctrl_ap_num 4 1
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for {set i 0} {1} {incr i} {
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set ERASEALLSTATUS [$dap apreg $ctrl_ap_num 8]
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if {$ERASEALLSTATUS == 0} {
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echo "\[$target\] device has been successfully erased and unlocked."
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break
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}
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if {$i == 0} {
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echo "Waiting for chip erase..."
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}
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if {$i >= 150} {
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echo "Error: \[$target\] recovery failed."
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break
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}
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sleep 100
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}
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# Assert reset
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$dap apreg $ctrl_ap_num 0 1
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# Deassert reset
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$dap apreg $ctrl_ap_num 0 0
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# Reset ERASEALL task
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$dap apreg $ctrl_ap_num 4 0
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if { $is_cpunet } {
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reset init
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} else {
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sleep 100
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$target arp_examine
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poll on
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}
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}
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lappend _telnet_autocomplete_skip _nrf_check_ap_lock _nrf_ctrl_ap_recover
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}
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@@ -0,0 +1,61 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# script for Nordic nRF51 series, a Cortex-M0 chip
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#
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source [find target/swj-dp.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME nrf51
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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# Work-area is a space in RAM used for flash programming
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# By default use 16kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x4000
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x0bb11477
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}
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swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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if {![using_hla]} {
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# The chip supports standard ARM/Cortex-M0 SYSRESETREQ signal
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cortex_m reset_config sysresetreq
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}
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flash bank $_CHIPNAME.flash nrf5 0x00000000 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.uicr nrf5 0x10001000 0 0 0 $_TARGETNAME
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# The chip should start up from internal 16Mhz RC, so setting adapter
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# clock to 1Mhz should be OK
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adapter speed 1000
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proc enable_all_ram {} {
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# nRF51822 Product Anomaly Notice (PAN) #16 explains that not all RAM banks
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# are reliably enabled after reset on some revisions (contrary to spec.) So after
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# resetting we enable all banks via the RAMON register
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mww 0x40000524 0xF
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}
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$_TARGETNAME configure -event reset-init { enable_all_ram }
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@@ -0,0 +1,184 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Nordic nRF52 series: ARM Cortex-M4 @ 64 MHz
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#
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source [find target/swj-dp.tcl]
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source [find mem_helper.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME nrf52
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}
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# Work-area is a space in RAM used for flash programming
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# By default use 16kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x4000
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x2ba01477
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}
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swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
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adapter speed 1000
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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if { [using_hla] } {
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echo ""
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echo "nRF52 device has a CTRL-AP dedicated to recover the device from AP lock."
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echo "A high level adapter (like a ST-Link) you are currently using cannot access"
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echo "the CTRL-AP so 'nrf52_recover' command will not work."
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echo "Do not enable UICR APPROTECT."
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echo ""
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} else {
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cortex_m reset_config sysresetreq
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$_TARGETNAME configure -event examine-fail nrf52_check_ap_lock
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}
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flash bank $_CHIPNAME.flash nrf5 0x00000000 0 1 1 $_TARGETNAME
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flash bank $_CHIPNAME.uicr nrf5 0x10001000 0 1 1 $_TARGETNAME
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# Test if MEM-AP is locked by UICR APPROTECT
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proc nrf52_check_ap_lock {} {
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set dap [[target current] cget -dap]
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set err [catch {set APPROTECTSTATUS [$dap apreg 1 0xc]}]
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if {$err == 0 && $APPROTECTSTATUS != 1} {
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echo "****** WARNING ******"
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echo "nRF52 device has AP lock engaged (see UICR APPROTECT register)."
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echo "Debug access is denied."
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echo "Use 'nrf52_recover' to erase and unlock the device."
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echo ""
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poll off
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}
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}
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# Mass erase and unlock the device using proprietary nRF CTRL-AP (AP #1)
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# http://www.ebyte.com produces modules with nRF52 locked by default,
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# use nrf52_recover to enable flashing and debug.
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proc nrf52_recover {} {
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set target [target current]
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set dap [$target cget -dap]
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set IDR [$dap apreg 1 0xfc]
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if {$IDR != 0x02880000} {
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echo "Error: Cannot access nRF52 CTRL-AP!"
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return
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}
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poll off
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# Reset and trigger ERASEALL task
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$dap apreg 1 4 0
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$dap apreg 1 4 1
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for {set i 0} {1} {incr i} {
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set ERASEALLSTATUS [$dap apreg 1 8]
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if {$ERASEALLSTATUS == 0} {
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echo "$target device has been successfully erased and unlocked."
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break
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}
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if {$i == 0} {
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echo "Waiting for chip erase..."
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}
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if {$i >= 150} {
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echo "Error: $target recovery failed."
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break
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}
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sleep 100
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}
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# Assert reset
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$dap apreg 1 0 1
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# Deassert reset
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$dap apreg 1 0 0
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# Reset ERASEALL task
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$dap apreg 1 4 0
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sleep 100
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$target arp_examine
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poll on
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}
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add_help_text nrf52_recover "Mass erase and unlock nRF52 device"
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tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
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lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
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proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname _chipname} {
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targets $_targetname
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# Read FICR.INFO.PART
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set PART [mrw 0x10000100]
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switch $PART {
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0x52840 -
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0x52833 -
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0x52832 {
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# Configuration values for all supported trace port speeds, see
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# TRACECONFIG.TRACEPORTSPEED
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set trace_port_speeds {
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32000000 0
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16000000 1
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8000000 2
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4000000 3
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}
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# Note that trace port clock stands for what is referred to as
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# TRACECLKIN in the Arm CoreSight documentation.
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set trace_port_clock [$_chipname.tpiu cget -traceclk]
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if { ![dict exists $trace_port_speeds $trace_port_clock] } {
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error "Trace clock speed is not supported"
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}
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# Set TRACECONFIG.TRACEPORTSPEED
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mmw 0x4000055C [dict get $trace_port_speeds $trace_port_clock] 0x3
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if { [$_chipname.tpiu cget -protocol] eq "sync" } {
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if { [$_chipname.tpiu cget -port-width] != 4 } {
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error "Device only supports 4-bit sync traces"
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}
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# Set TRACECONFIG.TRACEMUX to enable synchronous trace
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mmw 0x4000055C 0x00020000 0x00010000
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$_targetname configure -event reset-end {
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mmw 0x4000055C 0x00020000 0x00010000
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}
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} else {
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# Set TRACECONFIG.TRACEMUX to enable SWO
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mmw 0x4000055C 0x00010000 0x00020000
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$_targetname configure -event reset-end {
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mmw 0x4000055C 0x00010000 0x00020000
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}
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}
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}
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0x52820 -
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0x52811 -
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0x52810 -
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0x52805 {
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error "Device does not support TPIU"
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}
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default {
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error "Unknown device, cannot configure TPIU"
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}
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}
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}
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$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME $_CHIPNAME"
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@@ -0,0 +1,146 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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#
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# Nordic nRF53 series: dual ARM Cortex-M33, multidrop SWD
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#
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source [find target/swj-dp.tcl]
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source [find mem_helper.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME nrf53
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}
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# Work-area is a space in RAM used for flash programming
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# By default use 16kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x4000
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}
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x6ba02477
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}
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# Configurable instance ID resides in application UICR TINSTANCE
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if { [info exists SWD_INSTANCE_ID] } {
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set _SWD_INSTANCE_ID $SWD_INSTANCE_ID
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} else {
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set _SWD_INSTANCE_ID 0
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}
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swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
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if { [info exists SWD_MULTIDROP] } {
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -dp-id 0x0070289 -instance-id $_SWD_INSTANCE_ID
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} else {
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
|
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}
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set _TARGETNAME_APP $_CHIPNAME.cpuapp
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target create $_TARGETNAME_APP cortex_m -dap $_CHIPNAME.dap
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|
||||
$_TARGETNAME_APP configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
|
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|
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# The network core is not accessible over HLA
|
||||
if { ![using_hla] } {
|
||||
set _TARGETNAME_NET $_CHIPNAME.cpunet
|
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target create $_TARGETNAME_NET cortex_m -dap $_CHIPNAME.dap -ap-num 1 -defer-examine
|
||||
|
||||
targets $_TARGETNAME_APP
|
||||
|
||||
$_TARGETNAME_NET configure -work-area-phys 0x21000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
|
||||
}
|
||||
|
||||
# Keep adapter speed less or equal 2000 kHz or flash programming fails!
|
||||
adapter speed 1000
|
||||
|
||||
source [find target/nordic/common.cfg]
|
||||
|
||||
flash bank $_CHIPNAME.app.flash nrf5 0x00000000 0 0 0 $_TARGETNAME_APP
|
||||
flash bank $_CHIPNAME.app.uicr nrf5 0x00FF8000 0 0 0 $_TARGETNAME_APP
|
||||
|
||||
if { ![using_hla] } {
|
||||
|
||||
flash bank $_CHIPNAME.net.flash nrf5 0x01000000 0 0 0 $_TARGETNAME_NET
|
||||
flash bank $_CHIPNAME.net.uicr nrf5 0x01FF8000 0 0 0 $_TARGETNAME_NET
|
||||
|
||||
# System reset sets NETWORK.FORCEOFF which keeps the network core in reset
|
||||
# Don't touch network core during reset
|
||||
$_TARGETNAME_NET configure -event reset-assert {}
|
||||
# and start it after application core reset is finished to make all flash accessible
|
||||
$_TARGETNAME_APP configure -event reset-init "nrf53_cpunet_release $_CHIPNAME"
|
||||
|
||||
$_TARGETNAME_APP cortex_m reset_config sysresetreq
|
||||
$_TARGETNAME_NET cortex_m reset_config sysresetreq
|
||||
|
||||
$_TARGETNAME_APP configure -event examine-fail { _nrf_check_ap_lock 2 3 }
|
||||
$_TARGETNAME_NET configure -event examine-fail { _nrf_check_ap_lock 3 3 }
|
||||
|
||||
$_TARGETNAME_NET configure -event gdb-attach "_nrf53_cpunet_gdb_attach $_CHIPNAME"
|
||||
|
||||
proc _nrf53_cpunet_gdb_attach { _CHIPNAME } {
|
||||
set _TARGETNAME_APP $_CHIPNAME.cpuapp
|
||||
set _TARGETNAME_NET $_CHIPNAME.cpunet
|
||||
set RESET_NETWORK_FORCEOFF 0x50005614
|
||||
|
||||
set is_off [$_TARGETNAME_APP read_memory $RESET_NETWORK_FORCEOFF 32 1]
|
||||
if { $is_off } {
|
||||
nrf53_cpunet_release $_CHIPNAME
|
||||
$_TARGETNAME_NET arp_poll
|
||||
$_TARGETNAME_NET arp_waitstate halted 100
|
||||
} else {
|
||||
if { ![$_TARGETNAME_NET was_examined] } {
|
||||
$_TARGETNAME_NET arp_examine
|
||||
$_TARGETNAME_NET arp_poll
|
||||
}
|
||||
set s [$_TARGETNAME_NET curstate]
|
||||
if { ![string compare $s "halted"] } {
|
||||
halt
|
||||
}
|
||||
}
|
||||
}
|
||||
lappend _telnet_autocomplete_skip _nrf53_cpunet_gdb_attach
|
||||
|
||||
# Release the network core
|
||||
proc nrf53_cpunet_release { {_CHIPNAME nrf53} } {
|
||||
set _TARGETNAME_APP $_CHIPNAME.cpuapp
|
||||
set _TARGETNAME_NET $_CHIPNAME.cpunet
|
||||
set RESET_NETWORK_FORCEOFF 0x50005614
|
||||
set RESET_NETWORK_WORKAROUND 0x50005618
|
||||
set CORTEX_M_DCB_DEMCR 0xE000EDFC
|
||||
|
||||
$_TARGETNAME_APP mww $RESET_NETWORK_WORKAROUND 1
|
||||
$_TARGETNAME_APP mww $RESET_NETWORK_FORCEOFF 0
|
||||
$_TARGETNAME_APP mww $RESET_NETWORK_FORCEOFF 1
|
||||
set err [catch {$_TARGETNAME_NET arp_examine}]
|
||||
if { $err } {
|
||||
if { ![_nrf_check_ap_lock 3 3] } {
|
||||
echo "Error: \[$_TARGETNAME_NET\] examination failed"
|
||||
}
|
||||
return
|
||||
}
|
||||
# set TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET
|
||||
$_TARGETNAME_NET mww $CORTEX_M_DCB_DEMCR 0x01000501
|
||||
# Write DEMCR directly intead of permanetly setting by cortex_m vector_catch reset
|
||||
# following cortex_m_endreset_event() restores the original DEMCR value
|
||||
$_TARGETNAME_APP mww $RESET_NETWORK_FORCEOFF 0
|
||||
$_TARGETNAME_APP mww $RESET_NETWORK_WORKAROUND 0
|
||||
}
|
||||
|
||||
# Mass erase and unlock the device using proprietary nRF CTRL-AP (AP #2 or #3)
|
||||
proc nrf53_cpuapp_recover {} {
|
||||
_nrf_ctrl_ap_recover 2
|
||||
}
|
||||
add_help_text nrf53_cpuapp_recover "Mass erase flash and unlock nRF53 application CPU"
|
||||
|
||||
proc nrf53_recover {} {
|
||||
_nrf_ctrl_ap_recover 3 1
|
||||
}
|
||||
add_help_text nrf53_recover "Mass erase all device flash and unlock nRF53"
|
||||
}
|
||||
@@ -0,0 +1,67 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#
|
||||
# Nordic nRF54L series
|
||||
#
|
||||
# Arm Cortex-M33 processor with RISC-V coprocessor
|
||||
#
|
||||
# The device uses resistive RAM (RRAM) as non-volatile memory.
|
||||
#
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME nrf54l
|
||||
}
|
||||
|
||||
# Work-area is a space in RAM used for flash programming, by default use 16 KiB.
|
||||
if { [info exists WORKAREASIZE] } {
|
||||
set _WORKAREASIZE $WORKAREASIZE
|
||||
} else {
|
||||
set _WORKAREASIZE 0x4000
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x6ba02477
|
||||
}
|
||||
|
||||
# Multidrop instance ID should be configurable by FW in TAD TINSTANCE register.
|
||||
# Writes to the register are ignored due to a silicon erratum.
|
||||
if { [info exists SWD_INSTANCE_ID] } {
|
||||
set _SWD_INSTANCE_ID $SWD_INSTANCE_ID
|
||||
} else {
|
||||
set _SWD_INSTANCE_ID 0
|
||||
}
|
||||
|
||||
transport select swd
|
||||
|
||||
swd newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
|
||||
|
||||
if { [info exists SWD_MULTIDROP] } {
|
||||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -dp-id 0x001c0289 -instance-id $_SWD_INSTANCE_ID
|
||||
} else {
|
||||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
|
||||
}
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap -ap-num 0
|
||||
|
||||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
|
||||
|
||||
# Create target for the AUX access port (AUX-AP).
|
||||
target create $_CHIPNAME.aux mem_ap -dap $_CHIPNAME.dap -ap-num 1
|
||||
|
||||
# AUX-AP is accessible only if CSW Prot[0] bit (Data Access) is set
|
||||
$_CHIPNAME.dap apsel 1
|
||||
$_CHIPNAME.dap apcsw 0x01000000 0x01000000
|
||||
|
||||
adapter speed 1000
|
||||
|
||||
# Use main processor as default target.
|
||||
targets $_TARGETNAME
|
||||
|
||||
if {![using_hla]} {
|
||||
$_TARGETNAME cortex_m reset_config sysresetreq
|
||||
}
|
||||
@@ -0,0 +1,63 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
#
|
||||
# Nordic nRF91 series: ARM Cortex-M33, SWD only
|
||||
#
|
||||
|
||||
source [find target/swj-dp.tcl]
|
||||
source [find mem_helper.tcl]
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME nrf91
|
||||
}
|
||||
|
||||
# Work-area is a space in RAM used for flash programming
|
||||
# By default use 16kB
|
||||
if { [info exists WORKAREASIZE] } {
|
||||
set _WORKAREASIZE $WORKAREASIZE
|
||||
} else {
|
||||
set _WORKAREASIZE 0x4000
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x6ba02477
|
||||
}
|
||||
|
||||
swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
|
||||
|
||||
# Contrary to the product specification at least nRF9161 supports multidrop SWD.
|
||||
# The instance ID is fixed, no more than one nRF91 can be connected to one SWD bus.
|
||||
if { [info exists SWD_MULTIDROP] } {
|
||||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -dp-id 0x0090289 -instance-id 0
|
||||
} else {
|
||||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
|
||||
}
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
|
||||
|
||||
# Keep adapter speed less or equal 2000 kHz or flash programming fails!
|
||||
adapter speed 1000
|
||||
|
||||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
|
||||
|
||||
source [find target/nordic/common.cfg]
|
||||
|
||||
flash bank $_CHIPNAME.flash nrf5 0x00000000 0 0 0 $_TARGETNAME
|
||||
flash bank $_CHIPNAME.uicr nrf5 0x00FF8000 0 0 0 $_TARGETNAME
|
||||
|
||||
if { ![using_hla] } {
|
||||
$_TARGETNAME cortex_m reset_config sysresetreq
|
||||
|
||||
$_TARGETNAME configure -event examine-fail { _nrf_check_ap_lock 4 3 }
|
||||
}
|
||||
|
||||
# Mass erase and unlock the device using proprietary nRF CTRL-AP (AP #4)
|
||||
proc nrf91_recover {} {
|
||||
_nrf_ctrl_ap_recover 4
|
||||
}
|
||||
add_help_text nrf91_recover "Mass erase and unlock nRF91 device"
|
||||
Reference in New Issue
Block a user