Import xPack OpenOCD 0.12.0-7 and GNU Make 4.4.1 from x86_64-w64-mingw32.

2026-09-14 16:20:05 +08:00
parent 2b73c30a9d
commit 534c017e0f
1133 changed files with 74341 additions and 0 deletions
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+
+# Source the ESP common configuration file.
+source [find target/esp_common.cfg]
+
+# Target specific global variables
+set _CHIPNAME 					"esp32s3"
+set _CPUTAPID 					0x120034e5
+set _ESP_ARCH 					"xtensa"
+set _ONLYCPU					3
+set _ESP_SMP_TARGET				1
+set _ESP_SMP_BREAK 				1
+set _ESP_EFUSE_MAC_ADDR_REG  	0x60007044
+
+if { [info exists ESP32_S3_ONLYCPU] } {
+	set _ONLYCPU $ESP32_S3_ONLYCPU
+}
+
+proc esp32s3_memprot_is_enabled { } {
+	# SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG
+	if { [get_mmr_bit 0x600C10C0 0] != 0 } {
+		return 1
+	}
+	# SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG
+	if { [get_mmr_bit 0x600C1124 0] != 0 } {
+		return 1
+	}
+	# SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG
+	if { [get_mmr_bit 0x600C11D0 0] != 0 } {
+		return 1
+	}
+	# IRAM0, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG
+	if { [get_mmr_bit 0x600C10D8 0] != 0 } {
+		return 1
+	}
+	# DRAM0, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG
+	if { [get_mmr_bit 0x600C10FC 0] != 0 } {
+		return 1
+	}
+	# SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG
+	if { [get_mmr_bit 0x600C10E4 0] != 0 } {
+		return 1
+	}
+	# SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG
+	if { [get_mmr_bit 0x600C10F0 0] != 0 } {
+		return 1
+	}
+	# SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG
+	if { [get_mmr_bit 0x600C1104 0] != 0 } {
+		return 1
+	}
+	# SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG
+	if { [get_mmr_bit 0x600C1114 0] != 0 } {
+		return 1
+	}
+	# SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG
+	if { [get_mmr_bit 0x600C119C 0] != 0 } {
+		return 1
+	}
+	# SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG
+	if { [get_mmr_bit 0x600C1248 0] != 0 } {
+		return 1
+	}
+	return 0
+}
+
+proc esp32s3_soc_reset { } {
+	soft_reset_halt
+}
+
+create_esp_target $_ESP_ARCH
+
+source [find target/xtensa-core-esp32s3.cfg]