Import xPack OpenOCD 0.12.0-7 and GNU Make 4.4.1 from x86_64-w64-mingw32.

2026-09-14 16:20:05 +08:00
parent 2b73c30a9d
commit 534c017e0f
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+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# SAMA5D2 devices support both JTAG and SWD transports.
+#
+# The JTAG connection is disabled at reset, and during the ROM Code execution.
+# It is re-enabled when the ROM code jumps in the boot file copied from an
+# external Flash memory into the internalSRAM, or when the ROM code launches
+# the SAM-BA monitor, when no boot file has been found in any external Flash
+# memory.
+# For more JTAG related information see, :
+# https://ww1.microchip.com/downloads/en/DeviceDoc/SAMA5D2-Series-Data-sheet-ds60001476G.pdf
+#
+# If JTAGSEL pin:
+# - if enabled, boundary Scan mode is activated. JTAG ID Code value is 0x05B3F03F.
+# - if disabled, ICE mode is activated. Debug Port JTAG IDCODE value is 0x5BA00477
+#
+
+source [find target/swj-dp.tcl]
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		set _CPUTAPID 0x5ba00477
+	} else {
+		# SWD IDCODE (single drop, arm)
+		set _CPUTAPID 0x5ba02477
+	}
+}
+
+if { [info exists CHIPNAME] } {
+	set  _CHIPNAME $CHIPNAME
+} else {
+	set  _CHIPNAME at91sama5d2
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# Cortex-A5 target
+set _TARGETNAME $_CHIPNAME.cpu_a5
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 cortex_a -dap $_CHIPNAME.dap