Import xPack OpenOCD 0.12.0-7 and GNU Make 4.4.1 from x86_64-w64-mingw32.

2026-09-14 16:20:05 +08:00
parent 2b73c30a9d
commit 534c017e0f
1133 changed files with 74341 additions and 0 deletions
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Intel (Altera) Arria10 FPGA SoC
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME arria10
+}
+
+# ARM CoreSight Debug Access Port (dap HPS)
+if { [info exists DAP_TAPID] } {
+	set _DAP_TAPID $DAP_TAPID
+} else {
+	set _DAP_TAPID 0x4ba00477
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_DAP_TAPID
+
+# Subsidiary TAP: fpga (tap)
+# See Intel Arria 10 Handbook
+# https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/arria-10/a10_handbook.pdf
+# Intel Arria 10 GX 160  0x02ee20dd
+# Intel Arria 10 GX 220  0x02e220dd
+# Intel Arria 10 GX 270  0x02ee30dd
+# Intel Arria 10 GX 320  0x02e230dd
+# Intel Arria 10 GX 480  0x02e240dd
+# Intel Arria 10 GX 570  0x02ee50dd
+# Intel Arria 10 GX 660  0x02e250dd
+# Intel Arria 10 GX 900  0x02ee60dd
+# Intel Arria 10 GX 1150 0x02e660dd
+# Intel Arria 10 GT 900  0x02e260dd
+# Intel Arria 10 GT 1150 0x02e060dd
+# Intel Arria 10 SX 160  0x02e620dd
+# Intel Arria 10 SX 220  0x02e020dd
+# Intel Arria 10 SX 270  0x02e630dd
+# Intel Arria 10 SX 320  0x02e030dd
+# Intel Arria 10 SX 480  0x02e040dd
+# Intel Arria 10 SX 570  0x02e650dd
+# Intel Arria 10 SX 660  0x02e050dd
+jtag newtap $_CHIPNAME.fpga tap -irlen 10 -expected-id 0x02ee20dd -expected-id 0x02e220dd \
+	-expected-id 0x02ee30dd -expected-id 0x02e230dd -expected-id 0x02e240dd \
+	-expected-id 0x02ee50dd -expected-id 0x02e250dd -expected-id 0x02ee60dd \
+	-expected-id 0x02e660dd -expected-id 0x02e260dd -expected-id 0x02e060dd \
+	-expected-id 0x02e620dd -expected-id 0x02e020dd -expected-id 0x02e630dd \
+	-expected-id 0x02e030dd -expected-id 0x02e040dd -expected-id 0x02e650dd \
+	-expected-id 0x02e050dd
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+#
+# Cortex-A9 target
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 cortex_a -dap $_CHIPNAME.dap -coreid 0
+target create $_TARGETNAME.1 cortex_a -dap $_CHIPNAME.dap -coreid 1 \
+	-defer-examine
+target smp $_TARGETNAME.0 $_TARGETNAME.1