Import xPack OpenOCD 0.12.0-7 and GNU Make 4.4.1 from x86_64-w64-mingw32.
This commit is contained in:
@@ -0,0 +1,9 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# file altera-10m50.cfg replaced by altera-max10.cfg
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echo "DEPRECATED: use altera-max10.cfg instead of deprecated altera-10m50.cfg"
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#just to be backward compatible:
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#tap will be 10m50.tap instead of max10.tap:
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set CHIPNAME 10m50
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source [find cpld/altera-max10.cfg]
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@@ -0,0 +1,46 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Intel Arria II FPGA
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# Arria II Device Handbook
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# Table 11–2. 32-Bit IDCODE for Arria II Devices
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#GX:
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#EP2AGX45: 0x025120dd
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#EP2AGX65: 0x025020dd
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#EP2AGX95: 0x025130dd
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#EP2AGX125: 0x025030dd
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#EP2AGX190: 0x025140dd
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#EP2AGX260: 0x025040dd
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#EP2AGZ225: 0x024810dd
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#EP2AGZ300: 0x0240a0dd
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#EP2AGZ350: 0x024820dd
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME arriaii
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}
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array set _ARRIA_2_DATA {
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0x025120dd {1227 1174 EP2AGX45}
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0x025020dd {1227 -1 EP2AGX65}
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0x025130dd {1467 -1 EP2AGX95}
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0x025030dd {1467 -1 EP2AGX125}
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0x025140dd {1971 -1 EP2AGX190}
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0x025040dd {1971 -1 EP2AGX260}
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0x024810dd {2274 -1 EP2AGZ225}
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0x0240a0dd {2682 -1 EP2AGZ300}
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0x024820dd {2682 -1 EP2AGZ350}
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}
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set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version}
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foreach id [array names _ARRIA_2_DATA] {
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set cmd [concat "-expected-id" id]
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}
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eval $jtag_newtap_cmd
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source [find fpga/altera_common_init.cfg]
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pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family arriaii
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jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_ARRIA_2_DATA}"
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@@ -0,0 +1,36 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Intel Cyclone 10 FPGA
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# see: https://www.intel.com/content/www/us/en/docs/programmable/683777/current/bst-operation-control.html
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# and: https://www.intel.cn/content/dam/support/us/en/programmable/kdb/pdfs/literature/hb/cyclone-10/c10gx-51003.pdf
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME cyclone10
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}
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array set _CYCLONE_10_DATA {
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0x020f10dd { 603 226 10cl006_10cl010}
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0x020f20dd {1080 409 10cl016}
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0x020f30dd { 732 286 10cl025}
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0x020f40dd {1632 604 10cl040}
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0x020f50dd {1164 442 10cl055}
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0x020f60dd {1314 502 10cl080}
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0x020f70dd {1620 613 10cl120}
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0x02e120dd {1339 -1 GX085}
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0x02e320dd {1339 -1 GX105}
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0x02e720dd {1339 -1 GX150}
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0x02ef20dd {1339 -1 GX220}
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}
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set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version}
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foreach id [array names _CYCLONE_10_DATA] {
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set cmd [concat "-expected-id" id]
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}
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eval $jtag_newtap_cmd
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source [find fpga/altera_common_init.cfg]
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pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cyclone10
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jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_10_DATA}"
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@@ -0,0 +1,36 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Intel Cyclone III FPGA
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# see Cyclone III Device Handbook
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# Table 12-2: Device IDCODE for Cyclone III Device Family
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME cycloneiii
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}
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array set _CYCLONE_3_DATA {
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0x020f10dd { 603 226 EP3C5_EP3C10}
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0x020f20dd {1080 409 EP3C16}
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0x020f30dd { 732 286 EP3C25}
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0x020f40dd {1632 604 EP3C40}
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0x020f50dd {1164 442 EP3C55}
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0x020f60dd {1314 502 EP3C80}
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0x020f70dd {1620 613 EP3C120}
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0x027010dd {1314 226 EP3CLS70}
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0x027000dd {1314 226 EP3CLS100}
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0x027030dd {1314 409 EP3CLS150}
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0x027020dd {1314 409 EP3CLS200}
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}
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set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version}
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foreach id [array names _CYCLONE_3_DATA] {
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set cmd [concat "-expected-id" id]
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}
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eval $jtag_newtap_cmd
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source [find fpga/altera_common_init.cfg]
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pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cycloneiii
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jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_3_DATA}"
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@@ -0,0 +1,40 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Intel Cyclone IV FPGA
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# see Cyclone IV Device Handbook
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# Table 10-2: IDCODE Information for 32-Bit Cyclone IV Devices
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME cycloneiv
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}
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array set _CYCLON_4_DATA {
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0x020f10dd { 603 226 EP4CE6_EP4CE10}
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0x020f20dd {1080 409 EP4CE15}
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0x020f30dd { 732 286 EP4CE22}
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0x020f40dd {1632 604 EP4CE30_EP4CE40}
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0x020f50dd {1164 442 EP4CE55}
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0x020f60dd {1314 502 EP4CE75}
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0x020f70dd {1620 613 EP4CE115}
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0x028010dd { 260 229 EP4CGX15}
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0x028120dd { 494 463 EP4CGX22}
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0x028020dd { 494 463 EP4CGX30}
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0x028230dd {1006 943 EP4CGX30}
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0x028130dd {1006 943 EP4CGX50}
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0x028030dd {1006 943 EP4CGX75}
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0x028140dd {1495 1438 EP4CGX110}
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0x028040dd {1495 1438 EP4CGX150}
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}
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set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version}
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foreach id [array names _CYCLON_4_DATA] {
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set cmd [concat "-expected-id" id]
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}
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eval $jtag_newtap_cmd
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source [find fpga/altera_common_init.cfg]
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pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cycloneiv
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jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_4_DATA}"
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@@ -0,0 +1,39 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Intel Cyclone 5 FPGA
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# see Cyclone V Device Handbook
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# Table 9-1: IDCODE Information for Cyclone V Devices
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME cyclonev
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}
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array set _CYCLONE_5_DATA {
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0x02b150dd { 864 163 5CEA2}
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0x02d020dd {1485 19 5CSEA6_5CSXC6_5CSTD6}
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0x02b040dd {1728 -1 5CGXC9_5CGTD9}
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0x02b050dd { 864 163 5CEA4}
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0x02b030dd {1488 19 5CGXC7_5CGTD7}
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0x02d120dd {1485 -1 5CSEA5_5CSXC5_5CSTD5}
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0x02b220dd {1104 19 5CEA5}
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0x02b020dd {1104 19 5CGXC5_5CGTD5}
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0x02d010dd {1197 -1 5CSEA4_5CSXC4}
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0x02b120dd {1104 19 5CGXC4}
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0x02b140dd {1728 -1 5CEA9}
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0x02b010dd { 720 19 5CGXC3}
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0x02b130dd {1488 19 5CEA7}
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0x02d110dd {1197 -1 5CSEA2_5CSXC2}
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}
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set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version}
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foreach id [array names _CYCLONE_5_DATA] {
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set cmd [concat "-expected-id" id]
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}
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eval $jtag_newtap_cmd
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source [find fpga/altera_common_init.cfg]
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pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cyclonev
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jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_5_DATA}"
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@@ -0,0 +1,9 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# file altera-ep3c10.cfg replaced by altera-cycloneiii.cfg
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echo "DEPRECATED: use altera-cycloneiii.cfg instead of deprecated altera-ep3c10.cfg"
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#just to be backward compatible:
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#tap will be ep3c10.tap instead of cycloneiii.tap:
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set CHIPNAME ep3c10
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source [find fpga/altera-cycloneiii.cfg]
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@@ -0,0 +1,9 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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proc set_bscan_checkpos_on_setup {chipname data} {
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set tapid_w_version [jtag cget $chipname.tap -idcode]
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set version_mask 0x0fffffff
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set tapid [format 0x%08x [expr {$tapid_w_version & $version_mask}]]
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intel set_bscan $chipname.pld [lindex $data($tapid) 0]
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intel set_check_pos $chipname.pld [lindex $data($tapid) 1]
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}
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@@ -0,0 +1,23 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# efinix titanium
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# https://www.efinixinc.com/docs/an048-jtag-bst-titanium-v1.0.pdf
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME titanium
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}
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jtag newtap $_CHIPNAME tap -irlen 5 -ignore-version \
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-expected-id 0x10661A79 \
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-expected-id 0x00360A79 \
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-expected-id 0x10660A79 \
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-expected-id 0x00681A79 \
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-expected-id 0x00688A79 \
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-expected-id 0x00682A79 \
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-expected-id 0x0068CA79 \
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-expected-id 0x00680A79 \
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-expected-id 0x00684A79
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pld create $_CHIPNAME.pld efinix -chain-position $_CHIPNAME.tap -family titanium
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@@ -0,0 +1,17 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# efinix trion
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# https://www.efinixinc.com/docs/an021-jtag-bst-trion-v1.0.pdf
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME trion
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}
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jtag newtap $_CHIPNAME tap -irlen 4 -ignore-version \
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-expected-id 0x00210A79 \
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-expected-id 0x00240A79 \
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-expected-id 0x00220A79
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pld create $_CHIPNAME.pld efinix -chain-position $_CHIPNAME.tap -family trion
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@@ -0,0 +1,16 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# GateMateTM FPGA
|
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# https://www.colognechip.com/programmable-logic/gatemate/
|
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# https://colognechip.com/docs/ds1001-gatemate1-datasheet-latest.pdf
|
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME gatemate
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}
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jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
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-expected-id 0x20000001
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|
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pld create $_CHIPNAME.pld gatemate -chain-position $_CHIPNAME.tap
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@@ -0,0 +1,29 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
|
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|
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# Gowin FPGA IDCODEs
|
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# from JTAG Programming and Configuration Guide
|
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# http://cdn.gowinsemi.com.cn/TN653E.pdf
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME gw1n
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||||
}
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||||
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jtag newtap $_CHIPNAME tap -irlen 8 -ignore-version \
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-expected-id 0x0900281B \
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-expected-id 0x0900381B \
|
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-expected-id 0x0100681B \
|
||||
-expected-id 0x0300081B \
|
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-expected-id 0x0300181B \
|
||||
-expected-id 0x0120681B \
|
||||
-expected-id 0x0100381B \
|
||||
-expected-id 0x1100381B \
|
||||
-expected-id 0x0100981B \
|
||||
-expected-id 0x1100581B \
|
||||
-expected-id 0x1100481B \
|
||||
-expected-id 0x0100181B \
|
||||
-expected-id 0x1100181B \
|
||||
-expected-id 0x0100481B
|
||||
|
||||
pld create $_CHIPNAME.pld gowin -chain-position $_CHIPNAME.tap
|
||||
@@ -0,0 +1,18 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $_CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME certus
|
||||
}
|
||||
|
||||
# Lattice Certus
|
||||
#
|
||||
# Certus NX LFD2NX-17 0x310f0043
|
||||
# Certus NX LFD2NX-40 0x310f1043
|
||||
|
||||
|
||||
jtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \
|
||||
-expected-id 0x310F1043 -expected-id 0x310F0043
|
||||
|
||||
pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap
|
||||
@@ -0,0 +1,18 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $_CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME certuspro
|
||||
}
|
||||
|
||||
# Lattice CertusPro
|
||||
#
|
||||
# 0x010f4043 - LFCPNX-100
|
||||
# 0x 043 - LFCPNX-50
|
||||
|
||||
jtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \
|
||||
-expected-id 0x010f4043
|
||||
# -expected-id 0x01112043
|
||||
|
||||
pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap
|
||||
@@ -0,0 +1,31 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $_CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME ecp2
|
||||
}
|
||||
|
||||
# Lattice ECP2 family
|
||||
# TAP IDs are extracted from BSDL files found on this page:
|
||||
# https://www.latticesemi.com/Products/FPGAandCPLD/LatticeECP2M
|
||||
#
|
||||
# LFE2M20E: 0x01279043
|
||||
# LFE2M35E: 0x0127A043
|
||||
# LFE2M50E: 0x0127B043
|
||||
# LFE2M70E: 0x0127C043
|
||||
# LFE2M100E: 0x0127D043
|
||||
# LFEC2_6E: 0x01270043
|
||||
# LFEC2_12E: 0x01271043
|
||||
# LFEC2_20E: 0x01272043
|
||||
# LFEC2_35E: 0x01274043
|
||||
# LFEC2_50E: 0x01273043
|
||||
# LFEC2_70E: 0x01275043
|
||||
|
||||
jtag newtap $_CHIPNAME tap -irlen 8 \
|
||||
-expected-id 0x01279043 -expected-id 0x0127A043 -expected-id 0x0127B043 \
|
||||
-expected-id 0x0127C043 -expected-id 0x0127D043 -expected-id 0x01270043 \
|
||||
-expected-id 0x01271043 -expected-id 0x01272043 -expected-id 0x01274043 \
|
||||
-expected-id 0x01273043 -expected-id 0x01275043
|
||||
|
||||
pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap
|
||||
@@ -0,0 +1,22 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $_CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME ecp3
|
||||
}
|
||||
|
||||
# Lattice ECP3 family
|
||||
# TAP IDs are extracted from BSDL files found on this page:
|
||||
# https://www.latticesemi.com/Products/FPGAandCPLD/LatticeECP3
|
||||
#
|
||||
# LFE3_17: 0x01010043
|
||||
# LFE3_35: 0x01012043
|
||||
# LFE3_95: 0x01014043 and LFE3_70
|
||||
# LFE3_150: 0x01015043
|
||||
|
||||
jtag newtap $_CHIPNAME tap -irlen 8 \
|
||||
-expected-id 0x01010043 -expected-id 0x01012043 \
|
||||
-expected-id 0x01014043 -expected-id 0x01015043
|
||||
|
||||
pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap
|
||||
@@ -0,0 +1,30 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $_CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME ecp5
|
||||
}
|
||||
|
||||
# Lattice ECP5 family
|
||||
# TAP IDs are extracted from BSDL files found on this page:
|
||||
# https://www.latticesemi.com/Products/FPGAandCPLD/ECP5
|
||||
#
|
||||
# 0x01111043 - LAE5UM_25F/LFE5UM_25F
|
||||
# 0x01112043 - LAE5UM_45F/LFE5UM_45F
|
||||
# 0x01113043 - LAE5UM_85F/LFE5UM_85
|
||||
# 0x21111043 - LFE5U_12F
|
||||
# 0x41111043 - LFE5U_25F
|
||||
# 0x41112043 - LFE5U_45F
|
||||
# 0x41113043 - LFE5U_85F
|
||||
# 0x81111043 - LFE5UM5G-25
|
||||
# 0x81112043 - LFE5UM5G-45
|
||||
# 0x81113043 - LFE5UM5G-85
|
||||
|
||||
jtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \
|
||||
-expected-id 0x01111043 -expected-id 0x01112043 -expected-id 0x01113043 \
|
||||
-expected-id 0x21111043 -expected-id 0x41111043 -expected-id 0x41112043 \
|
||||
-expected-id 0x41113043 -expected-id 0x81111043 -expected-id 0x81112043 \
|
||||
-expected-id 0x81113043
|
||||
|
||||
pld create $_CHIPNAME.pld lattice -chain-position $_CHIPNAME.tap
|
||||
@@ -0,0 +1,53 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME machxo3
|
||||
}
|
||||
|
||||
# Lattice MachXO3 family
|
||||
# TAP IDs are extracted from BSDL files found on this page:
|
||||
# https://www.latticesemi.com/Products/FPGAandCPLD/MachXO3
|
||||
#
|
||||
# 0x412b2043 - LCMXO3L_1300E_XXUWG36/XXMG121
|
||||
# 0x412b3043 - LCMXO3L_2100E_XXMG121/XXMG256/XXUWG49
|
||||
# 0x412b4043 - LCMXO3L_4300E_XXMG121/XXMG324/XXUWG81
|
||||
# 0x412b5043 - LCMXO3L_6900E_XXMG256/XXMG324
|
||||
# 0x412b6043 - LCMXO3L_9400E_XXBG256/XXMG256
|
||||
# 0x412bb043 - LCMXO3L_2100C_XXBG256
|
||||
# 0x412bc043 - LCMXO3L_4300C_XXBG256/XXBG324
|
||||
# 0x412bd043 - LCMXO3L_6900C_XXBG256/XXBG324/XXBG400
|
||||
# 0x412be043 - LCMXO3L_9400C_XXBG256/XXBG400/XXBG484
|
||||
# 0x612b2043 - LCMXO3LF_1300E_XXMG121/XXUWG36
|
||||
# 0x612b3043 - LCMXO3LF_2100E_XXMG121/XXMG256/XXUWG49
|
||||
# 0x612b4043 - LCMXO3LF_4300E_XXMG121/XXMG256/XXMG324/XXUWG81
|
||||
# 0x612b5043 - LCMXO3LF_6900E_XXMG256/XXMG324
|
||||
# 0x612b6043 - LCMXO3LF_9400E_XXBG256/XXMG256
|
||||
# 0x612bb043 - LCMXO3LF_2100C_XXBG256
|
||||
# 0x612bc043 - LCMXO3LF_4300C_XXBG256/XXBG324
|
||||
# 0x612bd043 - LCMXO3LF_6900C_XXBG256/XXBG324/XXBG400
|
||||
# 0x612be043 - LCMXO3LF_9400C_XXBG256/XXBG400/XXBG484
|
||||
# 0xc12b2043 - LCMXO3L_640E_XXMG121
|
||||
# 0xc12b4043 - LCMXO3L_2100E_XXMG324
|
||||
# 0xc12bb043 - LCMXO3L_1300C_XXBG256/XXMG256
|
||||
# 0xc12bc043 - LCMXO3L_2100C_XXBG324
|
||||
# 0xc12bd043 - LCMXO3L_4300C_XXBG400
|
||||
# 0xe12b2043 - LCMXO3LF_640E_XXMG121
|
||||
# 0xe12b3043 - LCMXO3LF_1300E_XXMG256
|
||||
# 0xe12b4043 - LCMXO3LF_2100E_XXMG324
|
||||
# 0xe12bb043 - LCMXO3LF_1300C_XXBG256
|
||||
# 0xe12bc043 - LCMXO3LF_2100C_XXBG324
|
||||
# 0xe12bd043 - LCMXO3LF_4300C_XXBG400
|
||||
|
||||
jtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \
|
||||
-expected-id 0x412b2043 -expected-id 0x412b3043 -expected-id 0x412b4043 \
|
||||
-expected-id 0x412b5043 -expected-id 0x412b6043 -expected-id 0x412bb043 \
|
||||
-expected-id 0x412bc043 -expected-id 0x412bd043 -expected-id 0x412be043 \
|
||||
-expected-id 0x612b2043 -expected-id 0x612b3043 -expected-id 0x612b4043 \
|
||||
-expected-id 0x612b5043 -expected-id 0x612b6043 -expected-id 0x612bb043 \
|
||||
-expected-id 0x612bc043 -expected-id 0x612bd043 -expected-id 0x612be043 \
|
||||
-expected-id 0xc12b2043 -expected-id 0xc12b4043 -expected-id 0xc12bb043 \
|
||||
-expected-id 0xc12bc043 -expected-id 0xc12bd043 -expected-id 0xe12b2043 \
|
||||
-expected-id 0xe12b3043 -expected-id 0xe12b4043 -expected-id 0xe12bb043 \
|
||||
-expected-id 0xe12bc043 -expected-id 0xe12bd043
|
||||
@@ -0,0 +1,51 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
# Spartan3: Table 9-5 in https://www.xilinx.com/support/documentation/user_guides/ug332.pdf
|
||||
proc xilinx_dna_addr {chip} {
|
||||
array set addrs {
|
||||
Spartan3 0x31
|
||||
Spartan6 0x30
|
||||
Series7 0x17
|
||||
}
|
||||
return $addrs($chip)
|
||||
}
|
||||
|
||||
# Get the "Device DNA".
|
||||
# Most Xilinx FPGA devices contain an embedded, unique device identifier.
|
||||
# The identifier is nonvolatile, permanently programmed into
|
||||
# the FPGA, and is unchangeable providing a great serial / tracking number.
|
||||
# This function returns the DNA as a 64 bit integer with the 7 LSBs zeroed.
|
||||
# This is compatible with the FUSE DNA which contains all 64 bits.
|
||||
proc xilinx_get_dna {tap chip} {
|
||||
set XC7_ISC_ENABLE 0x10
|
||||
set XC7_ISC_DISABLE 0x16
|
||||
set XC7_ISC_DNA [xilinx_dna_addr $chip]
|
||||
|
||||
irscan $tap $XC7_ISC_ENABLE
|
||||
runtest 64
|
||||
irscan $tap $XC7_ISC_DNA
|
||||
scan [drscan $tap 32 0 32 0] "%08x %08x" hi lo
|
||||
runtest 64
|
||||
irscan $tap $XC7_ISC_DISABLE
|
||||
runtest 64
|
||||
# openocd interprets DR scans as LSB first, bit-reverse it
|
||||
return [scan [string reverse [format "%032b%032bb0" $lo $hi]] "%i"]
|
||||
}
|
||||
|
||||
# Print out the "Device DNA" in the same format that impact uses.
|
||||
proc xilinx_print_dna {dna} {
|
||||
set dna [expr {$dna >> 64 - 57}]
|
||||
echo [format "DNA = %057b (0x%016x)" $dna $dna]
|
||||
}
|
||||
|
||||
proc xc7_get_dna {tap} {
|
||||
return [xilinx_get_dna $tap Series7]
|
||||
}
|
||||
|
||||
proc xc6s_get_dna {tap} {
|
||||
return [xilinx_get_dna $tap Spartan6]
|
||||
}
|
||||
|
||||
proc xc3s_get_dna {tap} {
|
||||
return [xilinx_get_dna $tap Spartan3]
|
||||
}
|
||||
@@ -0,0 +1,161 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
# Xilinx XADC support for 7 Series FPGAs
|
||||
#
|
||||
# The 7 Series FPGAs contain an on-chip 12 bit ADC that can probe die
|
||||
# temperature, internal power supply rail voltages as well as external
|
||||
# voltages. The XADC is available both from fabric as well as through the
|
||||
# JTAG TAP.
|
||||
#
|
||||
# This code implements access through the JTAG TAP.
|
||||
#
|
||||
# https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf
|
||||
|
||||
# build a 32 bit DRP command for the XADC DR
|
||||
proc xadc_cmd {cmd addr data} {
|
||||
array set cmds {
|
||||
NOP 0x00
|
||||
READ 0x01
|
||||
WRITE 0x02
|
||||
}
|
||||
return [expr {($cmds($cmd) << 26) | ($addr << 16) | ($data << 0)}]
|
||||
}
|
||||
|
||||
# XADC register addresses
|
||||
# Some addresses (status registers 0-3) have special function when written to.
|
||||
proc XADC {key} {
|
||||
array set addrs {
|
||||
TEMP 0x00
|
||||
LOCK 0x00
|
||||
VCCINT 0x01
|
||||
VCCAUX 0x02
|
||||
VAUXEN 0x02
|
||||
VPVN 0x03
|
||||
RESET 0x03
|
||||
VREFP 0x04
|
||||
VREFN 0x05
|
||||
VCCBRAM 0x06
|
||||
SUPAOFFS 0x08
|
||||
ADCAOFFS 0x09
|
||||
ADCAGAIN 0x0a
|
||||
VCCPINT 0x0d
|
||||
VCCPAUX 0x0e
|
||||
VCCODDR 0x0f
|
||||
VAUX0 0x10
|
||||
VAUX1 0x11
|
||||
VAUX2 0x12
|
||||
VAUX3 0x13
|
||||
VAUX4 0x14
|
||||
VAUX5 0x15
|
||||
VAUX6 0x16
|
||||
VAUX7 0x17
|
||||
VAUX8 0x18
|
||||
VAUX9 0x19
|
||||
VAUX10 0x1a
|
||||
VAUX11 0x1b
|
||||
VAUX12 0x1c
|
||||
VAUX13 0x1d
|
||||
VAUX14 0x1e
|
||||
VAUX15 0x1f
|
||||
SUPBOFFS 0x30
|
||||
ADCBOFFS 0x31
|
||||
ADCBGAIN 0x32
|
||||
FLAG 0x3f
|
||||
CFG0 0x40
|
||||
CFG1 0x41
|
||||
CFG2 0x42
|
||||
SEQ0 0x48
|
||||
SEQ1 0x49
|
||||
SEQ2 0x4a
|
||||
SEQ3 0x4b
|
||||
SEQ4 0x4c
|
||||
SEQ5 0x4d
|
||||
SEQ6 0x4e
|
||||
SEQ7 0x4f
|
||||
ALARM0 0x50
|
||||
ALARM1 0x51
|
||||
ALARM2 0x52
|
||||
ALARM3 0x53
|
||||
ALARM4 0x54
|
||||
ALARM5 0x55
|
||||
ALARM6 0x56
|
||||
ALARM7 0x57
|
||||
ALARM8 0x58
|
||||
ALARM9 0x59
|
||||
ALARM10 0x5a
|
||||
ALARM11 0x5b
|
||||
ALARM12 0x5c
|
||||
ALARM13 0x5d
|
||||
ALARM14 0x5e
|
||||
ALARM15 0x5f
|
||||
}
|
||||
return $addrs($key)
|
||||
}
|
||||
|
||||
# Select the XADC DR
|
||||
proc xadc_select {tap} {
|
||||
set XADC_IR 0x37
|
||||
irscan $tap $XADC_IR
|
||||
runtest 10
|
||||
}
|
||||
|
||||
# XADC transfer
|
||||
proc xadc_xfer {tap cmd addr data} {
|
||||
set ret [drscan $tap 32 [xadc_cmd $cmd $addr $data]]
|
||||
runtest 10
|
||||
return [expr "0x$ret"]
|
||||
}
|
||||
|
||||
# XADC register write
|
||||
proc xadc_write {tap addr data} {
|
||||
xadc_xfer $tap WRITE $addr $data
|
||||
}
|
||||
|
||||
# XADC register read, non-pipelined
|
||||
proc xadc_read {tap addr} {
|
||||
xadc_xfer $tap READ $addr 0
|
||||
return [xadc_xfer $tap NOP 0 0]
|
||||
}
|
||||
|
||||
# convert 16 bit register code from ADC measurement on
|
||||
# external voltages (VAUX) to Volt
|
||||
proc xadc_volt {code} {
|
||||
return [expr {$code * 1./(1 << 16)}]
|
||||
}
|
||||
|
||||
# convert 16 bit temperature measurement to Celsius
|
||||
proc xadc_temp {code} {
|
||||
return [expr {$code * 503.975/(1 << 16) - 273.15}]
|
||||
}
|
||||
|
||||
# convert 16 bit suppply voltage measurement to Volt
|
||||
proc xadc_sup {code} {
|
||||
return [expr {$code * 3./(1 << 16)}]
|
||||
}
|
||||
|
||||
# perform a single channel measurement using default settings
|
||||
proc xadc_single {tap ch} {
|
||||
set cfg0 [xadc_read $tap [XADC CFG0]]
|
||||
set cfg1 [xadc_read $tap [XADC CFG1]]
|
||||
# set channel
|
||||
xadc_write $tap [XADC CFG0] $cfg0
|
||||
# single channel, disable the sequencer
|
||||
xadc_write $tap [XADC CFG1] 0x3000
|
||||
# leave some time for the conversion
|
||||
runtest 100
|
||||
set ret [xadc_read $tap [XADC $ch]]
|
||||
# restore CFG0/1
|
||||
xadc_write $tap [XADC CFG0] $cfg0
|
||||
xadc_write $tap [XADC CFG1] $cfg1
|
||||
return $ret
|
||||
}
|
||||
|
||||
# measure all internal voltages
|
||||
proc xadc_report {tap} {
|
||||
xadc_select $tap
|
||||
echo "TEMP [format %.2f [xadc_temp [xadc_single $tap TEMP]]] C"
|
||||
foreach ch [list VCCINT VCCAUX VCCBRAM VPVN VREFP VREFN \
|
||||
VCCPINT VCCPAUX VCCODDR] {
|
||||
echo "$ch [format %.3f [xadc_sup [xadc_single $tap $ch]]] V"
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,43 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
# Xilinx Spartan3 generation
|
||||
# https://www.xilinx.com/support/documentation/user_guides/ug331.pdf
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME xc3s
|
||||
}
|
||||
|
||||
# Table 12-4 in https://www.xilinx.com/support/documentation/user_guides/ug332.pdf
|
||||
# the 4 top bits (28:31) are the die stepping, ignore them.
|
||||
jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
|
||||
-expected-id 0x02210093 \
|
||||
-expected-id 0x02218093 \
|
||||
-expected-id 0x02220093 \
|
||||
-expected-id 0x02228093 \
|
||||
-expected-id 0x02230093 \
|
||||
-expected-id 0x02610093 \
|
||||
-expected-id 0x02618093 \
|
||||
-expected-id 0x02620093 \
|
||||
-expected-id 0x02628093 \
|
||||
-expected-id 0x02630093 \
|
||||
-expected-id 0x03840093 \
|
||||
-expected-id 0x0384E093 \
|
||||
-expected-id 0x01C10093 \
|
||||
-expected-id 0x01C1A093 \
|
||||
-expected-id 0x01C22093 \
|
||||
-expected-id 0x01C2E093 \
|
||||
-expected-id 0x01C3A093 \
|
||||
-expected-id 0x0140C093 \
|
||||
-expected-id 0x01414093 \
|
||||
-expected-id 0x0141C093 \
|
||||
-expected-id 0x01428093 \
|
||||
-expected-id 0x01434093 \
|
||||
-expected-id 0x01440093 \
|
||||
-expected-id 0x01448093 \
|
||||
-expected-id 0x01450093
|
||||
|
||||
pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
|
||||
|
||||
source [find fpga/xilinx-dna.cfg]
|
||||
Reference in New Issue
Block a user