Import xPack OpenOCD 0.12.0-7 and GNU Make 4.4.1 from x86_64-w64-mingw32.

2026-09-14 16:20:05 +08:00
parent 2b73c30a9d
commit 534c017e0f
1133 changed files with 74341 additions and 0 deletions
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+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is an STM32L496G discovery board with a single STM32L496AGI6 chip.
+# http://www.st.com/en/evaluation-tools/32l496gdiscovery.html
+
+# This is for using the onboard STLINK
+source [find interface/stlink.cfg]
+
+transport select swd
+
+# increase working area to 96KB
+set WORKAREASIZE 0x18000
+
+# enable stmqspi
+set QUADSPI 1
+
+source [find target/stm32l4x.cfg]
+
+# QUADSPI initialization
+proc qspi_init { } {
+	global a
+	mmw 0x4002104C 0x000001FF 0				;# RCC_AHB2ENR |= GPIOAEN-GPIOIEN (enable clocks)
+	mmw 0x40021050 0x00000100 0				;# RCC_AHB3ENR |= QSPIEN (enable clock)
+	sleep 1									;# Wait for clock startup
+
+	# PB11: BK1_NCS, PA03: CLK, PA06: BK1_IO3, PA07: BK1_IO2, PB00: BK1_IO1, PB01: BK1_IO0
+
+	# PA07:AF10:V, PA06:AF10:V, PA03:AF10:V, PB11:AF10:V, PB01:AF10:V, PB00:AF10:V
+
+	# Port A: PA07:AF10:V, PA06:AF10:V, PA03:AF10:V
+	mmw 0x48000000 0x0000A080 0x00005040    ;# MODER
+	mmw 0x48000008 0x0000F0C0 0x00000000    ;# OSPEEDR
+	mmw 0x48000020 0xAA00A000 0x55005000    ;# AFRL
+
+	# Port B: PB11:AF10:V, PB01:AF10:V, PB00:AF10:V
+	mmw 0x48000400 0x0080000A 0x00400005    ;# MODER
+	mmw 0x48000408 0x00C0000F 0x00000000    ;# OSPEEDR
+	mmw 0x48000420 0x000000AA 0x00000055    ;# AFRL
+	mmw 0x48000424 0x0000A000 0x00005000    ;# AFRH
+
+	mww 0xA0001030 0x00001000				;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
+	mww 0xA0001000 0x01500008				;# QUADSPI_CR: PRESCALER=1, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
+	mww 0xA0001004 0x00160100				;# QUADSPI_DCR: FSIZE=0x16, CSHT=0x01, CKMODE=0
+	mmw 0xA0001000 0x00000001 0				;# QUADSPI_CR: EN=1
+
+	# 1-line spi mode
+	mww 0xA0001014 0x000003F5				;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
+	sleep 1
+
+	# memory-mapped read mode with 3-byte addresses
+	mww 0xA0001014 0x0D002503				;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
+}
+
+$_TARGETNAME configure -event reset-init {
+	mmw 0x40022000 0x00000004 0x00000003	;# 4 WS for 72 MHz HCLK
+	sleep 1
+	mmw 0x40021000 0x00000100 0x00000000	;# HSI on
+	mww 0x4002100C 0x01002432				;# 72 MHz: PLLREN=1, PLLM=4, PLLN=36, PLLR=2, HSI
+	mww 0x40021008 0x00008001				;# always HSI, APB1: /1, APB2: /1
+	mmw 0x40021000 0x01000000 0x00000000	;# PLL on
+	sleep 1
+	mmw 0x40021008 0x00000003 0x00000000	;# switch to PLL
+	sleep 1
+
+	adapter speed 4000
+
+	qspi_init
+}