Import xPack OpenOCD 0.12.0-7 and GNU Make 4.4.1 from x86_64-w64-mingw32.

2026-09-14 16:20:05 +08:00
parent 2b73c30a9d
commit 534c017e0f
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+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Numato Mimas A7 - Artix 7 FPGA Board
+#
+# https://numato.com/product/mimas-a7-artix-7-fpga-development-board-with-ddr-sdram-and-gigabit-ethernet
+#
+# Note: Connect external DC power supply if programming a heavy design onto FPGA.
+#       Programming while powering via USB may lead to programming failure.
+#       Therefore, prefer external power supply.
+
+adapter driver ftdi
+ftdi device_desc "Mimas Artix 7 FPGA Module"
+ftdi vid_pid 0x2a19 0x1009
+
+# channel 0 is for custom purpose by users (like uart, fifo etc)
+# channel 1 is reserved for JTAG (by-default) or SPI (possible via changing solder jumpers)
+ftdi channel 1
+ftdi tdo_sample_edge falling
+
+
+# FTDI Pin Layout
+#
+# +--------+-------+-------+-------+-------+-------+-------+-------+
+# | DBUS7  | DBUS6 | DBUS5 | DBUS4 | DBUS3 | DBUS2 | DBUS1 | DBUS0 |
+# +--------+-------+-------+-------+-------+-------+-------+-------+
+# | PROG_B | OE_N  |  NC   |  NC   |  TMS  |  TDO  |  TDI  |  TCK  |
+# +--------+-------+-------+-------+-------+-------+-------+-------+
+#
+# OE_N is JTAG buffer output enable signal (active-low)
+# PROG_B is not used, so left as input to FTDI.
+#
+ftdi layout_init 0x0008 0x004b
+reset_config none
+adapter speed 30000
+
+source [find cpld/xilinx-xc7.cfg]
+source [find cpld/jtagspi.cfg]