Import xPack OpenOCD 0.12.0-7 and GNU Make 4.4.1 from x86_64-w64-mingw32.

2026-09-14 16:20:05 +08:00
parent 2b73c30a9d
commit 534c017e0f
1133 changed files with 74341 additions and 0 deletions
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+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Copyright 2010 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+#
+# under GPLv2 Only
+#
+# This is for the "at91rm9200-ek" eval board.
+#
+#
+# It has atmel at91rm9200 chip.
+source [find target/at91rm9200.cfg]
+
+reset_config trst_and_srst
+
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { at91rm9200_ek_init }
+
+## flash bank <name> <driver> <base> <size> <chip_width> <bus_width> <target>
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
+
+# The chip may run @ 32khz, so set a really low JTAG speed
+adapter speed 8
+
+proc at91rm9200_ek_init { } {
+	# Try to run at 1khz... Yea, that slow!
+	# Chip is really running @ 32khz
+	adapter speed 8
+
+	mww 0xfffffc64 0xffffffff
+	## disable all clocks but system clock
+	mww 0xfffffc04 0xfffffffe
+	## disable all clocks to pioa and piob
+	mww 0xfffffc14 0xffffffc3
+	## master clock = slow cpu = slow
+	## (means the CPU is running at 32khz!)
+	mww 0xfffffc30 0
+	## main osc enable
+	mww 0xfffffc20 0x0000ff01
+	## MC_PUP
+	mww 0xFFFFFF50 0x00000000
+	## MC_PUER: Memory controller protection unit disable
+	mww 0xFFFFFF54 0x00000000
+	## EBI_CFGR
+	mww 0xFFFFFF64 0x00000000
+	## SMC2_CSR[0]: 16bit, 2 TDF, 4 WS
+	mww 0xFFFFFF70 0x00003284
+
+	## Init Clocks
+	## CKGR_PLLAR
+	mww 0xFFFFFC28 0x2000BF05
+	## PLLAR: 179,712000 MHz for PCK
+	mww 0xFFFFFC28 0x20263E04
+	sleep 100
+	## PMC_MCKR
+	mww 0xFFFFFC30 0x00000100
+	sleep 100
+	## ;MCKR : PCK/3 = MCK Master Clock = 59,904000MHz from PLLA
+	mww 0xFFFFFC30 0x00000202
+	sleep 100
+
+	#========================================
+	# CPU now runs at 180mhz
+	# SYS runs at 60mhz.
+	adapter speed 40000
+	#========================================
+
+	## Init SDRAM
+	## PIOC_ASR: Configure PIOC as peripheral (D16/D31)
+	mww 0xFFFFF870 0xFFFF0000
+	## PIOC_BSR:
+	mww 0xFFFFF874 0x00000000
+	## PIOC_PDR:
+	mww 0xFFFFF804 0xFFFF0000
+	## EBI_CSA : CS1=SDRAM
+	mww 0xFFFFFF60 0x00000002
+	## EBI_CFGR:
+	mww 0xFFFFFF64 0x00000000
+	## SDRC_CR :
+	mww 0xFFFFFF98 0x2188c155
+	## SDRC_MR : Precharge All
+	mww 0xFFFFFF90 0x00000002
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## SDRC_MR : Refresh
+	mww 0xFFFFFF90 0x00000004
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## SDRC_MR : Load Mode Register
+	mww 0xFFFFFF90 0x00000003
+	## access SDRAM
+	mww 0x20000080 0x00000000
+	## SDRC_TR : Write refresh rate
+	mww 0xFFFFFF94 0x000002E0
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## SDRC_MR : Normal Mode
+	mww 0xFFFFFF90 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+}