commit for program flash script and specific OpenOCD config files for debugger interface and target chip architecture.

Tools/Specific_Config/cmsis-dap-interface.cfg

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+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# ARM CMSIS-DAP compliant adapter
+#
+# http://www.keil.com/support/man/docs/dapdebug/
+#
+
+adapter driver cmsis-dap
+
+# Optionally specify the serial number of CMSIS-DAP usb device.
+# adapter serial 02200201E6661E601B98E3B9

Tools/Specific_Config/stlink-interface.cfg

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+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# STMicroelectronics ST-LINK/V1, ST-LINK/V2, ST-LINK/V2-1, STLINK-V3 in-circuit
+# debugger/programmer
+#
+# This new interface driver creates a ST-Link wrapper for ARM-DAP named "dapdirect"
+# Old ST-LINK/V1 and ST-LINK/V2 pre version V2J24 don't support "dapdirect"
+#
+# SWIM transport is natively supported
+#
+
+if { [adapter name] == "hla" } {
+	# Deprecated HLA adapter driver already selected.
+	# Quit silently, as the ST-LINK driver already complains.
+	return
+}
+
+adapter driver st-link
+st-link vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b 0x0483 0x374d 0x0483 0x374e 0x0483 0x374f 0x0483 0x3752 0x0483 0x3753 0x0483 0x3754 0x0483 0x3755 0x0483 0x3757
+
+# transport select jtag
+# transport select swd
+# transport select swim
+
+# Optionally specify the serial number of usb device
+# e.g.
+# adapter serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f"

Tools/Specific_Config/stm32g0x-target.cfg

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+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# script for stm32g0x family
+
+#
+# stm32g0 devices support SWD transports only.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32g0x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# Smallest proposed target has 8kB ram, use 4kB by default to avoid surprises
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x1000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	# Section 37.5.5 - corresponds to Cortex-M0+
+	set _CPUTAPID 0x0bc11477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# 手动指定地址区间以支持 64K Flash
+flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0x10000 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.otp   stm32l4x 0x1fff7000 0       0 0 $_TARGETNAME
+
+# reasonable default
+adapter speed 2000
+
+adapter srst delay 100
+if {[using_jtag]} {
+	jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+	# if srst is not fitted use SYSRESETREQ to
+	# perform a soft reset
+	cortex_m reset_config sysresetreq
+}
+
+proc stm32g0x_default_reset_start {} {
+	# Reset clock is HSI16 (16 MHz)
+	adapter speed 2000
+}
+
+proc stm32g0x_default_examine_end {} {
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
+	mmw 0x40015804 0x00000006 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+	mmw 0x40015808 0x00001800 0
+}
+
+proc stm32g0x_default_reset_init {} {
+	# Increase clock to 64 Mhz
+	mmw 0x40022000 0x00000002 0x00000005	;# FLASH_ACR: Latency = 2
+	mww 0x4002100C 0x30000802				;# RCC_PLLCFGR = PLLR=/2, PLLN=8, PLLM=/1, PLLSRC=0x2
+	mmw 0x40021000 0x01000000 0x00000000	;# RCC_CR |= PLLON
+	mmw 0x40021008 0x00000002 0x00000005	;# RCC_CFGR: SW=PLLRCLK
+
+	# Boost JTAG frequency
+	adapter speed 4000
+}
+
+# Default hooks
+$_TARGETNAME configure -event examine-end { stm32g0x_default_examine_end }
+$_TARGETNAME configure -event reset-start { stm32g0x_default_reset_start }
+$_TARGETNAME configure -event reset-init { stm32g0x_default_reset_init }

program&flash.bat

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+@echo off
+:: call for build script
+call ".\make&build.bat" %*
+
+if NOT %errorlevel% == 0 (
+exit
+)
+
+@echo ================================[ StLink ]================================
+.\Tools\xpack-openocd-0.12.0-7\bin\openocd      ^
+-f .\Tools\Specific_Config\stlink-interface.cfg ^
+-f .\Tools\Specific_Config\stm32g0x-target.cfg  ^
+-c "program Build/Debug/STM32G030F6P6_Evaluation.elf verify reset exit"
+
+if %errorlevel% == 0 goto end
+
+@echo ================================[ CMSIS-DAP ]================================
+.\Tools\xpack-openocd-0.12.0-7\bin\openocd         ^
+-f .\Tools\Specific_Config\cmsis-dap-interface.cfg ^
+-f .\Tools\Specific_Config\stm32g0x-target.cfg     ^
+-c "program Build/Debug/STM32G030F6P6_Evaluation.elf verify reset exit"
+
+if %errorlevel% == 0 goto end
+
+@echo ================================[ STM32CubeProgrammer-Usart ]================================
+:: STM32G0x flash sector size：2K
+:: Uart mode can't erase flash memory over internal NVM size (32K). 
+:: Target flash MUST be erased first (try flash related functions or using debugger), otherwise the data can't be witten.
+:: Commands below erase all legal sectors manually and skip address check for allowing write data to extra hidden flash.
+STM32_Programmer_CLI.exe -c port=COM6 fc=hardware rts=high dtr=low -e [0 15] --skipErase -d .\Build\Release\STM32G030F6P6_Evaluation.elf
+STM32_Programmer_CLI.exe -c port=COM6 fc=hardware rts=low dtr=high -e [0 15] --skipErase -d .\Build\Release\STM32G030F6P6_Evaluation.elf
+
+if %errorlevel% == 0 (
+@echo ***** Need To Reset Target Manually *****
+goto end
+)
+
+@echo ================================[ Program Flash Failed ]================================
+
+exit
+
+:end
+@echo ================================[ Program Flash Accomplished ]================================